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DES_verilog
- this DES made by verilog
3des_verilog
- verilog 实现的3DES 和 DES 加解密算法，3DES目前还未被破解。-verilog implementation of 3DES and DES encryption and decryption algorithm, 3DES has yet to be cracked.
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
Barrel-shifter-design-report
- 实现变量移位操作的32-bit桶形移位寄存器；实现DES算法的数据路径设计及控制路径设计，有仿真和附录verilog代码 -Variable shift operations to achieve 32-bit barrel shifter implement the DES algorithm data path and control path design design
limited_des
- this DES encryption and decryption code in verilog-this is DES encryption and decryption code in verilog
My_DES3
- a triple-DES (Data Encryption Standard) hardware descr iption in verilog-HDL with testbench
s-box
- 用Verilog语言描述的des的s盒（des s盒 Verilog代码） -Verilog language descr iption des s box (des s box Verilog code)
DES_Verilog
- des加密算法verilog实现，包括模块定义，端口说明-des Encryption and decryption
Example-s5-1
- “\Example-s5-1\des” 目录下为设计工程，其设计输入采用Synplify预先编译好的.vqm网表 “\Example-s5-1\source”目录下为设计的源代码，这里只给出了Verilog语言实例，仅供读者参考 “\Example-s5-1\source \area_opt”目录下为面积优化的代码 “\Example-s5-1\source \perf_opt”目录下为性能优化的代码 “\Examp
DES_verilog
- 用verilog实现的DES(Data Encryption Standard数据加密标准)，把64位明文输入变为64位密文输出块。-Using DES (Data Encryption Standard Data Encryption Standard) verilog to achieve, the 64 plaintext input into 64 output ciphertext block.
des_latest.tar
- 利用verilog实现的DES和3DES两种加密算法，其中每个算法又利用了两种实现方式，分别是面积优先和性能优先-Both use DES and 3DES encryption algorithms verilog implementation, which took advantage of each algorithm implemented in two ways, which are the priority and performance priority area
DES_orginal_core
- this a DES encryption code in verilog-this is a DES encryption code in verilog